Volume 46, Nº 5 (2017)
- Ano: 2017
- Artigos: 10
- URL: https://journals.rcsi.science/1063-7397/issue/view/11677
Article
Simulating the chlorine plasma etching profile of high-aspect-ratio trenches in Si
Resumo
We simulate etching trenches in Si with a high (over 15) aspect ratio, i.e., the ratio between the trench depth and width in Cl2 plasma in wide ranges of the ratio between the flows of Cl atoms and Cl+ ions (3–300) and ion energies (50–250 eV). We demonstrate that the trenches with a high aspect (HA) ratio (~20) and almost vertical walls can be formed at the maximum energies of Ei = 250 eV and R = 300. At the lower values of these parameters, etching an HA-ratio trench is accompanied by its narrowing, curvature, or bending. We discuss the origin of the HA-trench bending effect at small R values and a high energy of the incident ions.
Peculiarities of the energy landscape of a rectangular magnetic nanoisland
Resumo
Micromagnetic modeling is used to study the energetics of magnetic switching of a rectangular single-layer permalloy nanoisland. The potential local energy minima of this system are found in the absence of an external field. The magnetization reversal along the long axis of the island is studied at different values of a constant transverse bias field. It is found that the presence of such a bias leads to a reduction of the longitudinal switching field. The energy landscape of the system is studied using the Nudged Elastic Band (NEB) method to shed more light on the nature of the effect. It is shown that the energy barrier for longitudinal switching is reduced with the growth of the magnitude of the transverse bias. This effect may have practical applications for optimizing MRAM technology, because it helps reduce the memory cell’s switching field.
Nonalloyed ohmic contacts for high-electron-mobility transistors based on AlGaN/GaN heterostructures
Resumo
A microwave field-effect transistor with nonalloyed ohmic contacts is fabricated using the technique of regrowing a heavily doped region under the contact metallization by molecular beam epitaxy through a preliminarily formed dielectric mask. The fabricated field-effect transistor with a gate length of 0.18 µm and a total width of 100 µm has a current–amplification cutoff frequency of 66 GHz and ohmic contact resistivity of 0.15-0.18 Ω mm.
Effect of diamond dicing of SiC device wafers on the technical and operational parameters of monolithic integrated circuits
Resumo
This paper is devoted to developing and optimizing the processing route that improves the effectiveness of diamond dicing of SiC device wafers with monolithic microwave integrated circuits (MMICs). The results of the experimental investigation of the diamond dicing effect on the MMIC parameters in the developed processing route are presented.
Silicide iridium sensors based on solid sensitive elements
Resumo
The experiments that have been carried out show that the times of adsorption and desorption depend both on the structure construction parameters and specific factors. This makes it possible to achieve the optimal time parameters of Ir–SiO2–Si structures by varying these factors.
Organizing the memory array of multiport register files to reduce power consumption
Resumo
This paper presents a method for designing the memory array of a multiport register file that makes it possible to reduce power consumption. The method is based on reorganizing the transistors in the read ports of a bitcell, as well as in the communication element between the local and global read bit lines. The method is adapted to the 28-nm technology. For comparative analysis, several layout variants were designed. For these layouts, by simulation, the power consumption values in the active mode and the leakage current values are obtained. As a result of the investigations, the active power consumption in the memory array is reduced by up to 19% and the leakage currents are reduced by 53% without loss of speed.
Low-noise amplifier for the range of 57–64 GHz with grounding holes through photolake layer
Resumo
This paper is devoted to the development of a low-noise amplifier for the range of 57–64 GHz based on a gallium nitride heterostructure. The test HEMT-transistors based on gallium nitride are measured, which made it possible to create the transistor models: the Fujii and Pospeshalskii models. The basic diagram of the amplifier, which is composed of 4 cascades, is designed and the full electrodynamic calculation of the topology is carried out in CAD ADS. The prepared sample is measured, which showed its working ability in the required frequency range (the gain is larger than 16 dB, the coefficient of noise is smaller than 6.5 dB), and a good agreement between the results of the calculations and measurements is found. The technological stage used for the formation of through holes, which provide the common grounding plane of the circuit elements, is described.
Investigation of the features of integrating nonvolatile FRAM elements with CMOS technology
Resumo
The results of the studies of the features of integrating the elements of nonvolatile ferroelectric random access memory (FRAM) with CMOS technology are presented. The possibility and prospects of using their nanosized layers in the elements of nonvolatile FRAM are demonstrated.
Modeling SiO2 leakage currents caused by electrical overloads
Resumo
A two-component model for the formation of leakage currents in SiO2 in a strong electric field is proposed. In the model, agreement is found between the theoretical and experimental values of leakage currents in a wide range of electric field strength and the size of charge transferred.
Small-signal optimization approach to design of microwave signal switch ICs on MOS transistors
Resumo
This paper presents a technique for optimizing small-signal parameters of monolithic microwave signal switches on MOS transistors. The technique is based on analytical expressions and visual plots that allow us to determine the topological sizes of transistors providing the optimal values of insertion losses and isolation (decoupling). The effect of the parasitic inductance of connecting bondwires on the characteristics of signal switches is investigated; it is shown that parasitic inductance has a minor effect on insertion losses and reflection losses, but causes severe degradation of isolation. Based on the proposed technique, an IP block for a monolithic microwave switch, which can be used as an antenna switch or a composite functional block in multibit step phase shifters and S- or C-band attenuators, is designed. The comparative results of the numerical simulation and experimental investigation of the 0.25 µm CMOS IP block are presented; at the frequency of 1 GHz, the block has an upper linearity bound of at least +17 dBm, insertion losses of not more than 0.6 dB, and isolation not worse than -37 dB.