Organizing the memory array of multiport register files to reduce power consumption
- Authors: Solovyeva L.A.1, Kirichenko P.G.1
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Affiliations:
- Scientific Research Institute of System Analysis
- Issue: Vol 46, No 5 (2017)
- Pages: 334-342
- Section: Article
- URL: https://journals.rcsi.science/1063-7397/article/view/186515
- DOI: https://doi.org/10.1134/S1063739717050109
- ID: 186515
Cite item
Abstract
This paper presents a method for designing the memory array of a multiport register file that makes it possible to reduce power consumption. The method is based on reorganizing the transistors in the read ports of a bitcell, as well as in the communication element between the local and global read bit lines. The method is adapted to the 28-nm technology. For comparative analysis, several layout variants were designed. For these layouts, by simulation, the power consumption values in the active mode and the leakage current values are obtained. As a result of the investigations, the active power consumption in the memory array is reduced by up to 19% and the leakage currents are reduced by 53% without loss of speed.
About the authors
L. A. Solovyeva
Scientific Research Institute of System Analysis
Author for correspondence.
Email: lsolov@cs.niisi.ras.ru
Russian Federation, Moscow, 117218
P. G. Kirichenko
Scientific Research Institute of System Analysis
Email: lsolov@cs.niisi.ras.ru
Russian Federation, Moscow, 117218