Small-signal optimization approach to design of microwave signal switch ICs on MOS transistors

Abstract

This paper presents a technique for optimizing small-signal parameters of monolithic microwave signal switches on MOS transistors. The technique is based on analytical expressions and visual plots that allow us to determine the topological sizes of transistors providing the optimal values of insertion losses and isolation (decoupling). The effect of the parasitic inductance of connecting bondwires on the characteristics of signal switches is investigated; it is shown that parasitic inductance has a minor effect on insertion losses and reflection losses, but causes severe degradation of isolation. Based on the proposed technique, an IP block for a monolithic microwave switch, which can be used as an antenna switch or a composite functional block in multibit step phase shifters and S- or C-band attenuators, is designed. The comparative results of the numerical simulation and experimental investigation of the 0.25 µm CMOS IP block are presented; at the frequency of 1 GHz, the block has an upper linearity bound of at least +17 dBm, insertion losses of not more than 0.6 dB, and isolation not worse than -37 dB.