Vol 48, No 4 (2019)

The published data on the atomic layer deposition of thin platinum-group metal (Ru, Rh, Pd, Os, Ir, and Pt) films with the use of different reactant precursors and second reactants (O₂, O₃, H₂, etc.) are generalized in the context of microelectronic technologies. A procedure for analyzing the data on the atomic layer deposition kinetics is discussed. The rate of atomic layer deposition of metallic ruthenium is not higher than 0.15 nm/cycle. An inverse dependence of the limiting atomic layer deposition growth rate on the precursor molecular mass is established. The rates of atomic layer deposition of thin films of all the remaining metals in the group range between 0.03–0.07 nm/cycle, which is lower than the values for a monolayer of these metals by several times. The methodology and ways of enhancing the reliability of the kinetic data on the atomic layer deposition are discussed, including the need for taking into account the sample surface types and effects of nucleation delays at the initial growth stages of the thin platinum-group metal film. The possible occurrence of chemical deposition reactions with intermediate products involved at the pulsed injection of the reactants is considered.

The process of the formation of silicon–nitrogen nanostructures at a GaAs surface with orientation (100) and (110) by atomic layer deposition (molecular layering) is considered. The synthesis ios carried out in a vacuum unit using SiCl₄ and NH₃ vapors in the temperature range 423–723 K with activation of the process by a glow discharge at the ammonia pulsing stage. The conditions of the growth of silicon nitride nanostructures and the conditions of a layer mechanism of their formation are determined. It is established that, at temperatures of synthesis above 573 K, the increase in the silicon nitride layer’s thickness reaches ≈0.5 nm/cycle, which is likely to be explained by the participation of hydrazine in the process of film formation.

The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing fault-tolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches.

The memristor pulse series oscillator based on the Schmitt trigger with a memristor and a capacitor at the input is discussed. It is shown that such circuit provides the generation of a pulse series the duration of which is determined by the amplitude of the input signal. The simulation results corroborate the wide functionality of the oscillator under discussion.

This article deals with a study of radiation-induced leakages between n-regions of various types using test structures fabricated according to the 0.18-µm CMOS technology. It is shown that, depending on the radiation exposure dose, the leakages between the n⁺-regions and the n-well may exceed the leakages between the n⁺-regions by 3–9 times, which should be taken into consideration when developing radiation resistant VSHICs.