Enviar artigo por via de e-mail Comparative Analysis of Double Gate Junction Less (DG JL) and Gate Stacked Double Gate Junction Less (GS DG JL) MOSFETs
- Autores: Shrey Arvind Singh 1, Shweta Tripathi 1
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Afiliações:
- Motilal Nehru National Institute of Technology
- Edição: Volume 53, Nº 13 (2019)
- Páginas: 1804-1810
- Seção: Physics of Semiconductor Devices
- URL: https://journals.rcsi.science/1063-7826/article/view/207465
- DOI: https://doi.org/10.1134/S1063782619130190
- ID: 207465
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Resumo
The quest for downscaling of devices has led to novel configurations with better performance parameters of which Junction Less (JL) MOSFET is an important configuration regarding its applicability. The JL MOSFETs have been analyzed for the physics behind its operation but a comparative study with the practically available devices is important from the point of view of further studies under the topic of JL MOSFETs. Further, the analytical modelling of GS DG JL MOSFETs is an analysis of crucial importance which has been discussed here.
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Sobre autores
Shrey Arvind Singh
Motilal Nehru National Institute of Technology
Email: shtri@mnnit.ac.in
Índia, Allahabad, Prayagraj, 211004
Shweta Tripathi
Motilal Nehru National Institute of Technology
Autor responsável pela correspondência
Email: shtri@mnnit.ac.in
Índia, Allahabad, Prayagraj, 211004
