Vol 48, No 3 (2019)
- Year: 2019
- Articles: 7
- URL: https://journals.rcsi.science/1063-7397/issue/view/11726
Article
Multilevel Bipolar Memristor Model Considering Deviations of Switching Parameters in the Verilog-A Language
Abstract
We describe a bipolar memristor in the Verilog-A language. The proposed model concepts take into account the following parameter deviations in the memristor switching between conduction states: the variation of the conduction parameters in the highly resistive and low-resistance state, the switching threshold variations, and the variation of the number of switching cycles.
Logical C-Element on STG DICE Trigger for Asynchronous Digital Devices Resistant to Single Nuclear Particles
Abstract
The results of the TCAD modeling of a new CMOS logical C-element are presented. The logic element of the bulk 65-nm CMOS technology based on a modified STG DICE trigger with reduced switching delay and two inverters with the third state is designed for high-speed asynchronous CMOS-logic systems with increased noise immunity to the impacts of single nuclear particles. The transistors of the element are spaced into two groups in such a way that the collection of charge from the track of a single nuclear particle by the transistors of only one of them cannot lead to a failure of the logical state of the C-element trigger in the mode of signal transmission from the element input to the output. The noise immunity can be increased by the separation of two groups of transistors at a distance that eliminates the simultaneous impact of a single nuclear particle on both groups of transistors. The charge collection from the tracks with a linear energy transfer of 60 MeV cm2/mg does not lead to failure of the logical function of the element and to failures in the transmission of common-mode logic signals by the C-element.
Monte Carlo Simulation of Defects of a Trench Profile in the Process of Deep Reactive Ion Etching of Silicon
Abstract
A numerical model of the evolution of a 2D profile during cryogenic etching of Si in SF6/O2 plasma is proposed and implemented. To calculate the fluxes of species a Monte Carlo method is used. The etch profile is presented with the help of square cells. The model is meant to investigate diverse defects in a profile of stochastic nature. For this, the state of a model cell is presented as a combination of states of several subcells randomly chosen upon each interaction of the species with the surface, which makes it possible to study small-scale profile defects without loss of calculation performance. They are compared with the experimental data, and good qualitative agreement is observed. Surface defects typical of high aspect ratio cryogenic etching are investigated numerically. They include the depth-dependent sidewall roughness, formation of cavities, trench splitting, and formation of “nanograss.”
Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate
Abstract
The technological rules and design standards have become much more complicated with the increase in the degree of integration of microelectronic systems and the reduction of the technological dimensions of the basic elements to 32 nm and smaller. There are several thousand design restrictions for technologies with transistor sizes of 32 nm and smaller. Compliance with the full set of rules and design standards in the automatic mode becomes impossible when using the existing approaches to solving problems of logical and topological synthesis. This leads to the need for a large amount of manual work with the editing scheme and topology at the final stage of verification of the project as a whole. The transition to the use of regular structures in the lower layers of the topology has solved the problem of the increasing number of design standards for technologies of 22 nm and below. Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve level for advanced technologies with a vertical transistor gate have been proposed in this paper. The method of the inter-vent resynthesis of circuits taking into account the specific of designing circuits on Fin FET transistors is proposed. The proposed approach combines the methods of logical resynthesis and structural optimization of the circuit in order to achieve the required parameters (area, fault tolerance, or taking into account the design features of VLSI). An algorithm for combining the fragments of the topology of the standard cells and blocks that were obtained as a result of inter-valve resynthesis taking into account the specifics of designing circuits on FinFET transistors is proposed.
Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip
Abstract
A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose circuits produced at PJSC “Mikron”. The developed methodology includes new techniques to solve layout synthesis problems at different design flow stages, including the initial circuit decomposition, placement of logical elements, and the interconnections routing. Presented design flow makes it possible to accelerate the development of large IP blocks for reconfigurable systems-on-chip with multiple types of switching elements and system-on-chip components.
Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit
Abstract
In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format. This problem arises in the process of layout versus schematic (LVS) verification, as well as when reengineering integrated circuits. A method for recognizing subcircuits (CMOS gates) is described. The method is implemented as a C++ program; it recognizes subcircuits that are described by the same logic functions but are not isomorphic at the transistor level as different ones. This provides the isomorphism of the original and decompiled circuits.
Reflection Spectra Modification of Diazoquinone-Novolak Photoresist Implanted with B and P Ions
Abstract
We investigate FP9120 positive photoresist films 1.8 μm thick that are spin-coated on the surface of KDB-10 (111) silicon wafers and implanted with В+ and Р+ ions by measuring the reflection’s spectra. It is shown that implantation reduces the refractive index of the photoresist. In the opacity region of the photoresist film, the reflection coefficient grows with an increasing implantation dose, especially in the case of P+ ion implantation. The spectral dependences of the optical length for the implanted photoresist films have two regions with anomalous dispersion near the wavelengths of 350 and 430 nm, which correspond to the absorption bands of naphthoquinone diazide molecules.