Logical C-Element on STG DICE Trigger for Asynchronous Digital Devices Resistant to Single Nuclear Particles

Abstract

The results of the TCAD modeling of a new CMOS logical C-element are presented. The logic element of the bulk 65-nm CMOS technology based on a modified STG DICE trigger with reduced switching delay and two inverters with the third state is designed for high-speed asynchronous CMOS-logic systems with increased noise immunity to the impacts of single nuclear particles. The transistors of the element are spaced into two groups in such a way that the collection of charge from the track of a single nuclear particle by the transistors of only one of them cannot lead to a failure of the logical state of the C-element trigger in the mode of signal transmission from the element input to the output. The noise immunity can be increased by the separation of two groups of transistors at a distance that eliminates the simultaneous impact of a single nuclear particle on both groups of transistors. The charge collection from the tracks with a linear energy transfer of 60 MeV cm²/mg does not lead to failure of the logical function of the element and to failures in the transmission of common-mode logic signals by the C-element.