Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit

Abstract

In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format. This problem arises in the process of layout versus schematic (LVS) verification, as well as when reengineering integrated circuits. A method for recognizing subcircuits (CMOS gates) is described. The method is implemented as a C++ program; it recognizes subcircuits that are described by the same logic functions but are not isomorphic at the transistor level as different ones. This provides the isomorphism of the original and decompiled circuits.