Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate

Abstract

The technological rules and design standards have become much more complicated with the increase in the degree of integration of microelectronic systems and the reduction of the technological dimensions of the basic elements to 32 nm and smaller. There are several thousand design restrictions for technologies with transistor sizes of 32 nm and smaller. Compliance with the full set of rules and design standards in the automatic mode becomes impossible when using the existing approaches to solving problems of logical and topological synthesis. This leads to the need for a large amount of manual work with the editing scheme and topology at the final stage of verification of the project as a whole. The transition to the use of regular structures in the lower layers of the topology has solved the problem of the increasing number of design standards for technologies of 22 nm and below. Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve level for advanced technologies with a vertical transistor gate have been proposed in this paper. The method of the inter-vent resynthesis of circuits taking into account the specific of designing circuits on Fin FET transistors is proposed. The proposed approach combines the methods of logical resynthesis and structural optimization of the circuit in order to achieve the required parameters (area, fault tolerance, or taking into account the design features of VLSI). An algorithm for combining the fragments of the topology of the standard cells and blocks that were obtained as a result of inter-valve resynthesis taking into account the specifics of designing circuits on FinFET transistors is proposed.