Vol 48, No 3 (2019)

The results of the TCAD modeling of a new CMOS logical C-element are presented. The logic element of the bulk 65-nm CMOS technology based on a modified STG DICE trigger with reduced switching delay and two inverters with the third state is designed for high-speed asynchronous CMOS-logic systems with increased noise immunity to the impacts of single nuclear particles. The transistors of the element are spaced into two groups in such a way that the collection of charge from the track of a single nuclear particle by the transistors of only one of them cannot lead to a failure of the logical state of the C-element trigger in the mode of signal transmission from the element input to the output. The noise immunity can be increased by the separation of two groups of transistors at a distance that eliminates the simultaneous impact of a single nuclear particle on both groups of transistors. The charge collection from the tracks with a linear energy transfer of 60 MeV cm²/mg does not lead to failure of the logical function of the element and to failures in the transmission of common-mode logic signals by the C-element.

The technological rules and design standards have become much more complicated with the increase in the degree of integration of microelectronic systems and the reduction of the technological dimensions of the basic elements to 32 nm and smaller. There are several thousand design restrictions for technologies with transistor sizes of 32 nm and smaller. Compliance with the full set of rules and design standards in the automatic mode becomes impossible when using the existing approaches to solving problems of logical and topological synthesis. This leads to the need for a large amount of manual work with the editing scheme and topology at the final stage of verification of the project as a whole. The transition to the use of regular structures in the lower layers of the topology has solved the problem of the increasing number of design standards for technologies of 22 nm and below. Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve level for advanced technologies with a vertical transistor gate have been proposed in this paper. The method of the inter-vent resynthesis of circuits taking into account the specific of designing circuits on Fin FET transistors is proposed. The proposed approach combines the methods of logical resynthesis and structural optimization of the circuit in order to achieve the required parameters (area, fault tolerance, or taking into account the design features of VLSI). An algorithm for combining the fragments of the topology of the standard cells and blocks that were obtained as a result of inter-valve resynthesis taking into account the specifics of designing circuits on FinFET transistors is proposed.

In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format. This problem arises in the process of layout versus schematic (LVS) verification, as well as when reengineering integrated circuits. A method for recognizing subcircuits (CMOS gates) is described. The method is implemented as a C++ program; it recognizes subcircuits that are described by the same logic functions but are not isomorphic at the transistor level as different ones. This provides the isomorphism of the original and decompiled circuits.