Stacked Gate FinFET with Gate Extension for Improved Gate Control

Abstract

Referring to the experimental data available, a modified pile gate bulk FinFET device with trapezoidal cross-section is analyzed through this paper. Two special features of Pile gate FinFET are trapezoidal cross-section and extended gate. The comprehensive performance metrics analysis justifies its improved performanceas compared to normal bulk FinFET. The device design analysis is also carried out for varying fin height, length of extension of the gate structure and bottom gate material work function. Thermal reliability is justified through analyzing electrical propertied for varying temperatures. The performance metrics considered for the analysis include threshold voltage, transconductance Subthreshold Slope, Drain Induced Barrier Lowering and Gate Induced Drain Leakage current.