Stacked Gate FinFET with Gate Extension for Improved Gate Control
- 作者: Sangeeta Mangesh 1, Chopra P.2, Saini K.3
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隶属关系:
- Department of Electronics Engineering JSS Academy of Technical Education
- Ajay Kumar Garg Engineering College
- National Physical Laboratories
- 期: 卷 47, 编号 6 (2018)
- 页面: 443-448
- 栏目: Article
- URL: https://journals.rcsi.science/1063-7397/article/view/186943
- DOI: https://doi.org/10.1134/S1063739718660010
- ID: 186943
如何引用文章
详细
Referring to the experimental data available, a modified pile gate bulk FinFET device with trapezoidal cross-section is analyzed through this paper. Two special features of Pile gate FinFET are trapezoidal cross-section and extended gate. The comprehensive performance metrics analysis justifies its improved performanceas compared to normal bulk FinFET. The device design analysis is also carried out for varying fin height, length of extension of the gate structure and bottom gate material work function. Thermal reliability is justified through analyzing electrical propertied for varying temperatures. The performance metrics considered for the analysis include threshold voltage, transconductance Subthreshold Slope, Drain Induced Barrier Lowering and Gate Induced Drain Leakage current.
作者简介
Sangeeta Mangesh
Department of Electronics Engineering JSS Academy of Technical Education
编辑信件的主要联系方式.
Email: sangeetamangesh@gmail.com
印度, Noida, UP, 201301
Pradeep Chopra
Ajay Kumar Garg Engineering College
Email: sangeetamangesh@gmail.com
印度, Ghaziabad, UP, 201009
Krishan Saini
National Physical Laboratories
Email: sangeetamangesh@gmail.com
印度, New Delhi, 110012