Mode optimization of retrograde pocket doping in SOI-MOS VLSI transistors

Abstract

A two-stage optimization technique for the parameters of SOI-MOS structures is proposed based on the correction of the pocket formation modes of an active structure. As a result of the use of this technique, the threshold voltage of the bottom (parasitic) transistor doubles, while maintaining the values of the parameters of the upper (main) transistor. The experimental investigations confirmed the effectiveness of using this optimization technique when doping the pockets of a SOI-MOS structure to provide the radiation hardness to the accumulated dose.