电邮这篇文章 An 8-bit parallel DAC with segmented architecture
- 作者: Enuchenko M.1, Morozov D.1, Pilipko M.1
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隶属关系:
- Peter the Great St. Petersburg Polytechnic University
- 期: 卷 62, 编号 1 (2017)
- 页面: 89-100
- 栏目: Novel Radio Systems and Elements
- URL: https://journals.rcsi.science/1064-2269/article/view/197920
- DOI: https://doi.org/10.1134/S1064226917010053
- ID: 197920
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详细
An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.
作者简介
M. Enuchenko
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
俄罗斯联邦, Politekhnicheskaya ul. 29, St. Petersburg, 195251
D. Morozov
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
俄罗斯联邦, Politekhnicheskaya ul. 29, St. Petersburg, 195251
M. Pilipko
Peter the Great St. Petersburg Polytechnic University
编辑信件的主要联系方式.
Email: mixeme@outlook.com
俄罗斯联邦, Politekhnicheskaya ul. 29, St. Petersburg, 195251
