Enviar artigo por via de e-mail An 8-bit parallel DAC with segmented architecture
- Autores: Enuchenko M.S.1, Morozov D.V.1, Pilipko M.M.1
-
Afiliações:
- Peter the Great St. Petersburg Polytechnic University
- Edição: Volume 62, Nº 1 (2017)
- Páginas: 89-100
- Seção: Novel Radio Systems and Elements
- URL: https://journals.rcsi.science/1064-2269/article/view/197920
- DOI: https://doi.org/10.1134/S1064226917010053
- ID: 197920
Citar
Acesso aberto
Acesso está concedido
Somente assinantes
Resumo
An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.
Sobre autores
M. Enuchenko
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
Rússia, Politekhnicheskaya ul. 29, St. Petersburg, 195251
D. Morozov
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
Rússia, Politekhnicheskaya ul. 29, St. Petersburg, 195251
M. Pilipko
Peter the Great St. Petersburg Polytechnic University
Autor responsável pela correspondência
Email: mixeme@outlook.com
Rússia, Politekhnicheskaya ul. 29, St. Petersburg, 195251
Arquivos suplementares
