Email this article An 8-bit parallel DAC with segmented architecture
- Authors: Enuchenko M.S.1, Morozov D.V.1, Pilipko M.M.1
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Affiliations:
- Peter the Great St. Petersburg Polytechnic University
- Issue: Vol 62, No 1 (2017)
- Pages: 89-100
- Section: Novel Radio Systems and Elements
- URL: https://journals.rcsi.science/1064-2269/article/view/197920
- DOI: https://doi.org/10.1134/S1064226917010053
- ID: 197920
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Abstract
An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.
About the authors
M. S. Enuchenko
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
Russian Federation, Politekhnicheskaya ul. 29, St. Petersburg, 195251
D. V. Morozov
Peter the Great St. Petersburg Polytechnic University
Email: mixeme@outlook.com
Russian Federation, Politekhnicheskaya ul. 29, St. Petersburg, 195251
M. M. Pilipko
Peter the Great St. Petersburg Polytechnic University
Author for correspondence.
Email: mixeme@outlook.com
Russian Federation, Politekhnicheskaya ul. 29, St. Petersburg, 195251
