Integration of functional elements of resistive nonvolative memory with 1T-1R topology

Abstract

The issues related to the integration of functional elements of ReRAM memory based on resistive Pt/HfO₂/TiN structures with transistors fabricated by CMOS technology (0.18 μm node) are discussed when placing the memory cells in metallization layers. It is shown that the formation of a ReRAM stack can be organized as the “back end of line” (BEOL) process. The possibility is demonstrated of writing information in fabricated 1T-1R cells at the given levels of current determined by the voltage on the transistor, which allows one to choose the required values of resistance for the ON and OFF states. The presence of a transistor makes it possible to limit the power that is scattered in a resistance-switchable structure, and makes its parameters virtually insensitive to changes in the voltage of writing. The latter circumstance makes it possible to use the same recording voltage for all devices, which makes the problem of reproducing the values for different cells in an array less acute.