Simulation of Single Event Effects in STG DICE Memory Cells

Abstract

TCAD simulation of single event effects in memory cells with transistors spaced into two groups (spaced transistor groups—STG DICE) is carried out on the set of test tracks passing through the drains of mutually sensitive CMOS transistors from one group and between the two groups at depths of 50–850 nm from the chip surface. When the charge from the track affects only one group of transistors, no upsets occur; in this case, the duration of the unsteady state is described by a linear function with a coefficient of 1.3–2.4 ps/(MeV cm²/mg) for tracks 50–350 nm deep and a coefficient of 11–12 ps/(MeV cm²/mg) for tracks 450–850 nm deep, with the linear energy transfer on the tracks ranging from 1 to 60 MeV cm²/mg in both cases. An upset of the logical state of the STG DICE cell can occur when the particle tracks follow the line connecting the two groups of transistors and when angular deviations from it are in the range of 40°. With the track normal to the chip surface, an upset can occur when the linear energy transfer exceeds 50–60 MeV cm²/mg.