Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration
- Authors: Baranov G.V.1,2, Milenin A.P.3, Baklanov M.P.3
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Affiliations:
- Molecular Electronics Research Institute SC
- Moscow Institute of Physics and Technology (State University)
- IMEC
- Issue: Vol 45, No 3 (2016)
- Pages: 186-190
- Section: Article
- URL: https://journals.rcsi.science/1063-7397/article/view/185620
- DOI: https://doi.org/10.1134/S1063739716030033
- ID: 185620
Cite item
Abstract
The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the “fin” structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies.
About the authors
G. V. Baranov
Molecular Electronics Research Institute SC; Moscow Institute of Physics and Technology (State University)
Author for correspondence.
Email: baranov@phystech.edu
Russian Federation, Zelenograd; Dolgoprudny
A. P. Milenin
IMEC
Email: baranov@phystech.edu
Belgium, Leuven
M. P. Baklanov
IMEC
Email: baranov@phystech.edu
Belgium, Leuven