Email this article Cyclic pipeline systems
- Authors: Adamovich I.A.1, Klimov Y.A.2
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Affiliations:
- Ailamazyan Program Systems Institute of RAS
- Keldysh Institute of Applied Mathematics of RAS
- Issue: Vol 14, No 4 (2023)
- Pages: 67-89
- Section: Articles
- URL: https://journals.rcsi.science/2079-3316/article/view/259989
- DOI: https://doi.org/10.25209/2079-3316-2023-14-4-67-89
- ID: 259989
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Abstract
One of the most efficient ways to organize calculations on ASIC or FPGA is the creation of non-stallable pipelines. However, for some computing circuits, the resulting pipeline may be too large for available ASIC or FPGA resources. The authors propose a method for constructing cyclic pipelines, in which data flow control is based on counters and does not depend on the data being transmitting along the pipeline. We proposed the method makes it possible to build more compact non-stallable pipelines. One of the main details of method is to use cycle ratio equal to the number of times the data must go through the loop, after which the pipeline converts the data into the desired result.
Keywords
About the authors
Igor Alekseevich Adamovich
Ailamazyan Program Systems Institute of RAS
Author for correspondence.
Email: i.a.adamovich@gmail.com
ORCID iD: 0000-0001-9728-3024
Yuri Andreevich Klimov
Keldysh Institute of Applied Mathematics of RAS
Email: yuklimov@keldysh.ru
ORCID iD: 0000-0001-5081-1547
References
- Taraate V.. Logic Synthesis and SOC Prototyping, Springer, Singapore, 2020, ISBN 978-981-15-1313-8, xix+251 pp.
- Kilts S.. Advanced FPGA Design: Architecture, Implementation, and Optimization, Wiley-IEEE Press, 2007, ISBN 9780470127896, 352 pp.
- Андреев С. С., Дбар С. А., Лацис А. О, Плоткина Е. А.. Как и почему могут быть использованы на практике суперкомпьютеры на базе FPGA, РАН, М., 2017, ISBN 978-5-906906-61-8, 40 с.
- Dally W. J., Harting R. C.. Digital Design: A Systems Approach, Cambridge University Press, 2012, ISBN 978-0-521-19950-6, 636 pp.
- Harris S. L., Harris D.. Digital Design and Computer Architecture, RISC-V Edition, Elseiver Inc, 2022, ISBN 978-0-12-820064-3, 592 pp.
- Intel$^{circledR}$ Hyperflex$^{{TM}}$ Architecture High-Performance Design Handbook, Intel Corporation, 2021, 147 pp.
- Emas M. N., Baylis A., Stitt G.. “High-frequency absorption-FIFO pipelining for Stratix 10 HyperFlex”, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (Boulder, CO, USA, 2018), 2018, pp. 97–100.
- LogiCORE IP Multiplier v11.2, Xilinx, Inc, 2011, 13 pp.
- LogiCORE IP Floating-Point Operator v6.0, Xilinx, Inc, 2012, 41 pp.
- Андреев С. С., Дбар С. А., Лацис А. О., Плоткина Е. А.. «О применении технологий высокоуровневого синтеза к схемной реализации вычислений», Препринты ИПМ им. М.В. Келдыша, 2021, 34, 19 с.
- Ioannou L., Michail H. E., Voyiatzis A. G.. “High performance pipelined FPGA implementation of the SHA-3 hash algorithm”, 2015 4th Mediterranean Conference on Embedded Computing (MECO) (Budva, Montenegro, 2015), 2015, pp. 68-71.
- Wong M. M., Haj-Yahya J., Sau S. Chattopadhyay A.. “A new high throughput and area efficient SHA-3 implementation”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (Florence, Italy, 2018), 2018, pp. 1-5.
- Vivado Design Suite: AXI Reference Guide, Xilinx, Inc, 2017, 175 pp.
- Avalon$^{circledR}$ Interface Specifications, Intel Corporation, 2022, 71 pp.
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