A sample and hold device

Abstract

Typical sample and hold devices (SHDs) are characterized by a number of drawbacks: zero offset at the SHD output caused mainly by the zero-offset voltage of the operational amplifiers that are parts of the SHD, significant sampling time due to the need to use a storage capacitor with the largest possible capacity to increase the storage time, and the uncertainty of the sampling time conditioned by the recharge mode of the storage capacitor, which is a commutation process with nonzero initial conditions of a random character. An attempt to stabilize the sampling time with simultaneous minimization resulted in the development of an accelerated recharging procedure for the SHD storage capacitor based on amplification of the input signal, forced recharging of the storage capacitor, and determination of the amplitude equity moment of the memorized analogue system and the SHD output signal.