Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip


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详细

A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose circuits produced at PJSC “Mikron”. The developed methodology includes new techniques to solve layout synthesis problems at different design flow stages, including the initial circuit decomposition, placement of logical elements, and the interconnections routing. Presented design flow makes it possible to accelerate the development of large IP blocks for reconfigurable systems-on-chip with multiple types of switching elements and system-on-chip components.

作者简介

S. Gavrilov

Institute for Design Problems in Microelectronics, Russian Academy of Sciences

编辑信件的主要联系方式.
Email: sergey_g@ippm.ru
俄罗斯联邦, Zelenograd, Moscow, 124365

D. Zheleznikov

Institute for Design Problems in Microelectronics, Russian Academy of Sciences

编辑信件的主要联系方式.
Email: zheleznikov_d@ippm.ru
俄罗斯联邦, Zelenograd, Moscow, 124365

M. Zapletina

Institute for Design Problems in Microelectronics, Russian Academy of Sciences

Email: venns@niime.ru
俄罗斯联邦, Zelenograd, Moscow, 124365

V. Khvatov

Institute for Design Problems in Microelectronics, Russian Academy of Sciences

Email: venns@niime.ru
俄罗斯联邦, Zelenograd, Moscow, 124365

R. Chochaev

Institute for Design Problems in Microelectronics, Russian Academy of Sciences

Email: venns@niime.ru
俄罗斯联邦, Zelenograd, Moscow, 124365

V. Enns

Molecular Electronics Research Institute (JSC “NIIME”)

编辑信件的主要联系方式.
Email: venns@niime.ru
俄罗斯联邦, Zelenograd, Moscow, 124460


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