Methods of Improving the Accuracy of Simulating Delays and Peak Currents of Combinational CMOS-Circuits at the Logical Design Level

With the reduction of the technological dimensions of transistors, the influence of the variations of circuit and technological parameters on the values of the delay of the elements of combinational CMOS-circuits has grown significantly. Due to the spread of the values of these parameters, the uncertainty of delays appears, which leads to the necessity to define the ranges of possible delay values. The peak current in power lines when switching the inputs of gates is another factor increasingly influencing the design process of CMOS circuits in the transition to nanometer technologies. The value of the peak current is used to estimate the voltage drop in the power lines, which in turn is necessary to calculate the width of the power lines of CMOS circuits and switch off the transistors in the method of reducing the static power. The methods of full circuit simulation do not comprehensively analyze the circuits with a large number of inputs and the methods at the logical level of designing CMOS circuits do not provide the desired accuracy of the evaluation of the values of the delays and the peak current in the circuit. The problem of increasing the accuracy and the reliability of the analysis of the performance and peak currents of CMOS combinational circuits, taking into account the simultaneous switching of the inputs, as well as the analysis of logical correlations of the signals, is considered. The proposed method is based on using the cubic approximation of the correction difference of delays, taking into account the simultaneous switching of inputs. It is shown that the developed techniques of the analysis of the performance and peak currents of CMOS combinational circuits improve the accuracy of the upper estimates of the analyzed parameters by up to 3% compared with accurate simulation and make it possible to reduce the pessimistic upper estimate by factors of 2 to 3 compared with the estimate of the worst case. The developed methods of improving the accuracy of simulating delays and peak currents of combinational CMOS-circuits can be used as an addition to the existing CADS tools for VLSI for noise-immunity analysis, the analysis of the peak currents, characterization of complex functional units, and improving the accuracy of classical static analysis. To improving the accuracy of the interval estimates of the minimum delays and maximum peak current, the simulation methods taking into account the simultaneous switching of the inputs of the logical element are developed. In relation to the circuit simulation, the error of these methods does not exceed 3%. Compared with the results obtained without taking the simultaneous switching into account, reducing the minimum delay by up to 50% and the pessimistic estimate of the peak current of combinational circuits is reduced on average by 50–55%.