Simulation the Effects of Single Nuclear Particles on STG RS Triggers with Transistors Spacing into Two Groups

Abstract

An RS trigger with a structure of transistors separated into two groups (spaced transistor groups (STGs) RS trigger) is developed and the TCAD simulation of this logical element is performed by the bulk CMOS technology with a designed size of 65 nm. The tolerance of an RS trigger to the effect of single nuclear particles is improved by separating its transistors into two groups such that the impact on one of these groups does not lead to the upset of the logical state of this trigger. In an STG RS trigger, the collection of a charge from particle tracks oriented along the normal to the crystal surface does not result in an upset during the linear energy transfer within the range of up to 50 (MeV cm²)/mg. An increase in the distance between these two groups leads to the growth of tolerance to upsets. No upsets occur in the case of topology with alternating groups of neighboring RS triggers during linear on-track energy transfers of 100 (MeV cm²)/mg. The data reading elements of 65-nm CMOS blocks of content-addressable memory (CAM) are developed based on the STG RS trigger.