Email this article Automated Generation of Machine Instruction Decoders
- Authors: Fokina N.Y.1, Solovev M.A.1
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Affiliations:
- Ivannikov Institute for System Programming, Russian Academy of Sciences
- Issue: Vol 45, No 7 (2019)
- Pages: 390-397
- Section: Article
- URL: https://journals.rcsi.science/0361-7688/article/view/176942
- DOI: https://doi.org/10.1134/S0361768819070065
- ID: 176942
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Abstract
A method for the automated generation of machine instruction decoders for a wide range of processor architectures that uses the target architecture assembler is proposed. A software tool based on this method is implemented and tested on a number of microcontrollers, such as PIC16F877A, AVR, Tricore, and H8/300H.
About the authors
N. Yu. Fokina
Ivannikov Institute for System Programming, Russian Academy of Sciences
Author for correspondence.
Email: nfokina@ispras.ru
Russian Federation, Moscow, 109004
M. A. Solovev
Ivannikov Institute for System Programming, Russian Academy of Sciences
Author for correspondence.
Email: icee@ispras.ru
Russian Federation, Moscow, 109004
