Automated Generation of Machine Instruction Decoders


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详细

A method for the automated generation of machine instruction decoders for a wide range of processor architectures that uses the target architecture assembler is proposed. A software tool based on this method is implemented and tested on a number of microcontrollers, such as PIC16F877A, AVR, Tricore, and H8/300H.

作者简介

N. Fokina

Ivannikov Institute for System Programming, Russian Academy of Sciences

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Email: nfokina@ispras.ru
俄罗斯联邦, Moscow, 109004

M. Solovev

Ivannikov Institute for System Programming, Russian Academy of Sciences

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Email: icee@ispras.ru
俄罗斯联邦, Moscow, 109004

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