Ways to set up a concurrent error detection system for logical circuits without memory

Abstract

Classical and modulo codes with summation of active bits of data vectors are often used to set up a concurrent error detection system for logical circuits without memory. Due to specificity in code generation, the number of ways for organizing the concurrent error detection system is equal to the number of inputs of the tested object. The task of expending the set of codes with summation has appeared. Methods of digital device theory, coding theory, and technical diagnostic theory are used for solving this problem. The generalized algorithm for generating the generic class of modulo modified code with summing of the active bits of data vectors is presented and the set’s cardinality is determined for the given number of outputs of the tested object. The essence of the presented class of codes lies in the determination of the smallest nonnegative deductions of a data vector’s weight and correction of the obtained modified weights. Modulo modified codes with summing of the active bits of data vectors are characterized by different properties of error detection in functional diagnostic systems. This makes it possible to generate dependable digital devices with reduced hardware redundancy and power consumption.