Data processing in the firmware systems for logic control based on search networks


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It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.

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V. Sklyarov

Universidade Aveiro, Instituto di Electrónica et Informática

编辑信件的主要联系方式.
Email: skl@ua.pt
葡萄牙, Aveiro

I. Skliarova

Universidade Aveiro, Instituto di Electrónica et Informática

Email: skl@ua.pt
葡萄牙, Aveiro

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