Short Complete Fault Detection Tests for Logic Networks with Fan-In Two
- Authors: Popkov K.A.1
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Affiliations:
- Keldysh Institute of Applied Mathematics
- Issue: Vol 13, No 1 (2019)
- Pages: 118-131
- Section: Article
- URL: https://journals.rcsi.science/1990-4789/article/view/213150
- DOI: https://doi.org/10.1134/S1990478919010137
- ID: 213150
Cite item
Abstract
It is established that we can implement almost every Boolean function on n variables by a logic network in the basis {x&y, x ∨ y, x ⨁ y, 1}, allowing a complete fault detection test with length at most 4 under arbitrary stuck-at faults at outputs of gates. The following assertions are also proved:We can implement each Boolean function on n variables by a logic network in the basis {x&y, x ∨ y, x ⨁ y, 1} (in the basis {x&y, x ∨ y, x ∨ y, x ⨁ y}) containing at most one dummy variable and allowing a complete fault detection test of length at most 5 (at most 4, respectively) under faults of the same type.
About the authors
K. A. Popkov
Keldysh Institute of Applied Mathematics
Author for correspondence.
Email: kirill-formulist@mail.ru
Russian Federation, Miusskaya pl. 4, Moscow, 125047
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