Minimizing the Finite-State Machines by Using the Values of Input Variables for Coding the Internal States

Abstract

This article describes a method of synthesizing finite-state machines (FSMs) on programmable logic devices (PLDs) while using the values of the input variables for coding the internal states. For this purpose, it is suggested to combine the structural models of FSMs of class A and E. The method of synthesizing a combined FSM model of AE class, which consists of splitting the internal states for fulfilling the necessary conditions of synthesizing an E-class machine and coding the internal states of an AE-class machine, is discussed. It is shown that this method allows reducing the cost of implementing FSMs for various families of PLDs by up to factors of 1.57 to 2.33 for binary coding and 3.00 for unary coding. This method also allows increasing the operation speed by up to 1.22–1.59 factors for binary coding and 1.34–2.93 for unary coding. In conclusion, recommendations are given regarding the practical use of the method, and possible areas for further development are suggested.