Estimation of the energy consumption of digital devices represented by a composition of a control FSM and an arithmetic and logic unit

Abstract

It is proposed to estimate the energy consumption of logic circuits implementing digital devices using the results of rapid modeling of both the structure descriptions of logic circuits and the original algorithmic descriptions of the devices by which the logic circuits are designed. The energy consumption estimation is reduced to finding power-hungry test suites that cause increased energy consumption. Two methods for the algorithmic description of digital devices are proposed. The algorithmic descriptions are used to design logic circuits that differ in energy consumption, area, and speed. The experiments show that the proper description of the device operation at the algorithmic level helps significantly reduce its energy consumption.