电邮这篇文章 Computing Observability of Gates in Combinational Logic Circuits by Bit-Parallel Simulation
- 作者: Telpukhov D.V.1, Nadolenko V.V.2, Gurov S.I.3
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隶属关系:
- Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
- Institute for Design Problems in Microelectronics (IPPM RAS)
- Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
- 期: 卷 30, 编号 2 (2019)
- 页面: 177-190
- 栏目: Article
- URL: https://journals.rcsi.science/1046-283X/article/view/247865
- DOI: https://doi.org/10.1007/s10598-019-09445-y
- ID: 247865
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详细
The article considers vector computation methods (bit-parallel simulation) for determining the observability of combinational logic gates. The computations produce an ODC (observability don’t care) set of all gates for a given set of circuit states. These results make it possible to evaluate the probability of logical masking of a random circuit fault. The methods are compared by accuracy and time costs using testing results for ISCAS ’85 benchmark circuits.
作者简介
D. Telpukhov
Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
编辑信件的主要联系方式.
Email: nofrost@inbox.ru
俄罗斯联邦, Moscow
V. Nadolenko
Institute for Design Problems in Microelectronics (IPPM RAS)
Email: nofrost@inbox.ru
俄罗斯联邦, Moscow
S. Gurov
Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
Email: nofrost@inbox.ru
俄罗斯联邦, Moscow
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