Enviar artigo por via de e-mail Computing Observability of Gates in Combinational Logic Circuits by Bit-Parallel Simulation
- Autores: Telpukhov D.V.1, Nadolenko V.V.2, Gurov S.I.3
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Afiliações:
- Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
- Institute for Design Problems in Microelectronics (IPPM RAS)
- Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
- Edição: Volume 30, Nº 2 (2019)
- Páginas: 177-190
- Seção: Article
- URL: https://journals.rcsi.science/1046-283X/article/view/247865
- DOI: https://doi.org/10.1007/s10598-019-09445-y
- ID: 247865
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Resumo
The article considers vector computation methods (bit-parallel simulation) for determining the observability of combinational logic gates. The computations produce an ODC (observability don’t care) set of all gates for a given set of circuit states. These results make it possible to evaluate the probability of logical masking of a random circuit fault. The methods are compared by accuracy and time costs using testing results for ISCAS ’85 benchmark circuits.
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Sobre autores
D. Telpukhov
Head of the ICDM Department, Institute for Design Problems in Microelectronics (IPPM RAS)
Autor responsável pela correspondência
Email: nofrost@inbox.ru
Rússia, Moscow
V. Nadolenko
Institute for Design Problems in Microelectronics (IPPM RAS)
Email: nofrost@inbox.ru
Rússia, Moscow
S. Gurov
Faculty of Computational Mathematics and Cybernetics, Lomonosov Moscow State University
Email: nofrost@inbox.ru
Rússia, Moscow
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