Economic Modelling and Implementation of Test Signal Generator for Characterization of Continuous Time Sigma-Delta Analog-to-Digital Converter

详细

Now there is a tremendous growth in the specific applications positively related to wireless communications, which posses the specific requirement for mixed-signal integrated circuits. When these independent circuits are used in the unique design of ADC and DAC practical applications, the considerable complexity of the testing increases. BIST is a precisely conventional technique which typically reduces this considerable complexity and prevents functional dependence on high-cost test equipment ATE. Moreover, in Built-In-self-Test (BIST), the output response analyzer (ORA) is the most significant component of architecture of continuous time (CT) sigma-delta analog-to-digital converter (ADC). There are numerous techniques of ORA used for accurate determining the design parameters like integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise ratio (SNR). In this paper, the prime focus is primarily on the modern CORDIC technique which is used as ORA. For the modelling and accurate simulation of this technique Matlab simulink and CADENCE VIRTUOSO EDA tool environment software are properly implemented. A Coordinate Rotation Digital Computer (CORDIC) reduces the design complexity of the independent circuit. The design of ADC can be improved tremendously by typically using BIST. This paper focuses on the system level modelling of test stimuli generator (TSG) and its simulation for accurate characterization of high-resolution sigma-delta ADC. The successful implementation is carefully tested on Matlab simulink tool environment. The auto-testing external test equipment is required to test the integrated structures. TSG is implemented and it helps in extracting of statics and transmission parameters required for characterization of CT sigma-delta ADC.