Enhanced Static Noise Margin and Increased Stability SRAM Cell with Emerging Device Memristor at 45-nm Technology

Abstract

Very Large Scale Integrated (VLSI) technology has conquered a momentous transformation and adaption. The glory of achieving these platforms goes to aspect ratio shrinking. Not only the dimensions are scaling down, but the revolution is forcing the designers to switch all circuits from one device level to another emerging devices. In this conflict, memristors are capable of making their roots stronger in VLSI domain as compared to other emerging devices. In this paper it is presented the research of static noise margin, highlighting the new fidelity issue i.e. the noise that has great impact on retention voltage of SRAM cell and this effect in memristive cell is less as compared to conventional 7T SRAM cell. Simulations and results have been performed and obtained from 7T SRAM and memristive 7T SRAM cell at 45 nm technology. In this paper, impact of the cell and pull-up ratio with their comparisons is also discussed.