Implementation of complex digital PLL for phase detection in software defined radar

Abstract

Software defined radar (SDR) has been the latest trend in developing enhanced radar signal processing techniques for state-of-the-art radar systems. SDR provides tremendous flexibility in reconfigurable design and rapid prototyping capabilities on FPGA platform. To cater real-time processing for high-speed radar, COordinate Rotation Digital Computer (CORDIC) unit has been utilized as a core processing element in a complex digital phase locked loop (DPLL) for digital demodulation of received signal. Since the real-time systems are required to handle extremely high sampling rates, the pipelined architecture of CORDIC processing element has been chosen for its inherent high system throughput. The architecture is optimized in terms of bit-length for better convergence and loop performance of the first order complex DPLL during demodulation. TheBOXCARfilter has been used as a low pass filter in the output stage of the detector for better information recovery from narrow samples with little energy signal without incurring hardware overhead. Extensive MATLAB simulations have been added to show the effectiveness of the design for the application of radar phase detection.